The present disclosure relates to semiconductor memory devices, such as non-volatile semiconductor memory devices etc., and more particularly, to ferroelectric random access memory (FeRAM) devices which can store data after being subjected to, for example, a high-temperature thermal treatment, and semiconductor integrated circuits including FeRAM devices.
In recent years, attention has been paid to non-volatile semiconductor memory, such as ferroelectric random access memory (FeRAM or FRAM), erasable and programmable read only memory (EPROM), electrical erasable and programmable read only memory (EEPROM), etc.
For these memory devices, the microfabrication techniques have been advanced, the memory capacity has been increased, and the voltage has been lowered. Therefore, the amount of charge stored per bit has decreased. The stored charge amount further decreases under a high-temperature environment etc., so that stored data may fail to be read out.
Conventional memory devices have addressed the failure or error by error detection using data duplication or parity checking, error correction using a majority decision circuit or an ECC circuit, etc.
Japanese Patent Publication No. H11-96781 describes a conventional technique relating to the present disclosure, and more specifically, a semiconductor memory device in which a particular one(s) of a plurality of memory sectors is set as a highly reliable region. When write operation is performed in the region, two or more memory cells are simultaneously written. When read operation is performed, the memory cells which have been simultaneously written are simultaneously read.
Due to this, the number of times the non-volatile semiconductor memory device can be rewritten can be increased, and the decrease in cell current can be reduced even if the storage time is elongated. In this technique, the cell currents of memory cells are added together. The size of the memory sector in the highly reliable region is externally adjusted.
Here, the simultaneous write/read control of two or more memory cells and the adjustment of the memory sector size are performed by changing the logic process of an address signal input to an address decoder.
Japanese Patent Publication No. 2007-073141 describes another conventional technique relating to the present disclosure, and more specifically, a semiconductor memory in which regions having different specifications are provided in a memory region, and one of the regions is selected, depending on the desired specifications.
In the above technique, the memory region including the same cells is separated into a first memory region which operates in a volatile mode and a second memory region which operates in a non-volatile mode, depending on the specifications of timing of internal operation. An operation control circuit controls the time during which a voltage is applied to a plate line, based on a signal output from an operation switching circuit, to select the first memory region (volatile mode operation) or the second memory region (non-volatile mode operation), which is then accessed.
Japanese Patent Publication No. H06-52697 also describes a conventional technique relating to the present disclosure, and more specifically, a semiconductor memory device with an error correction function. The semiconductor memory device includes memory cell array sections including an odd number of three or more memory cells, and majority decision circuits for the respective memory cell array sections, thereby correcting an error in a memory cell.
However, in Japanese Patent Publication No. H11-96781, two or more memory cells are simultaneously selected by changing the logic process of an address signal input to an address decoder. Therefore, a decoding circuit is required in order to provide such an address decoding function, resulting in an increase in the size of the decoding circuit.
In Japanese Patent Publication No. 2007-073141, data write/read operation is performed on single-bit memory cells. Therefore, a data storage characteristic is determined based on a characteristic of a memory cell which is a 1-bit unit, and therefore, in particular, data loss caused by stress (a high-temperature treatment etc.) after storage of data cannot be avoided only by switching timing specifications (data which can be correctly read out cannot be ensured).
Moreover, in Japanese Patent Publication No. H06-52697, error detection can correct only correctable errors.
Error correction for multiple bits requires a complicated circuit for error correction.
The semiconductor memory device with an error correction function of Japanese Patent Publication No. H06-52697 requires memory cell array sections including an odd number of three or more memory cells, and majority decision circuits for the respective memory cell array sections.